The present invention relates to a turbo-code decoder and, more particularly, to a high-speed turbo-code decoder with low power consumption, which is suitable for a portable telephone LSI (Large Scale Integrated circuit).
Conventionally, soft decision on decoding of error correction used for land mobile communication systems or the like is becoming an essential function because of its high coding gain, as is represented by a soft decision Viterbi decoder. In recent years, a new coding method called turbo-code encoding that attains the correcting performance close to the Shannon limit is disclosed in Berrou et al, NEAR SHANNON LIMIT ERROR-CORRECTING CODING AND DECODING: TURBO-CODES (1)xe2x80x3, Proceeding of International Conference of Communication, pp. 1064-1070, May 1993 (reference 1).
For land mobile communication systems of next generation, wide band multimedia communications for not only voice data but also the high-speed Internet or moving image are expected to flourish, and demand has arisen for a new scheme capable of providing these communications as mobile multimedia services. Under these circumstances, application of turbo-codes to the next-generation land mobile communication systems has been actively examined. To apply turbo-codes to a portable telephone or the like in consideration of wide band multimedia communication, a high-speed turbo-code decoder with low power consumption must be implemented.
It is an object of the present invention to provide a turbo-code decoder, i.e., a decoding scheme having higher performance than that of soft decision Viterbi decoding, in a form suitable for a mobile information terminal represented by a portable telephone so as to provide a high-speed turbo-code decoder with low power consumption.
In order to achieve the above object, according to the present invention, there is provided a turbo-code decoder comprising a first reception signal memory for storing an information sequence, a second reception signal memory for storing first and second parity sequences, an a priori memory for storing extrinsic/previous information in repetitive processing, a first adder for adding the information sequence read out from the first reception signal memory and the previous information read out from the a priori memory, first selection means for selecting one of the first and second parity sequences read out from the second reception signal memory, and second selection means for, on the basis of a polarity of a calculation result from the first adder and a polarity of a selection output from the first selection means, selecting one of the sum from the first adder including a negative polarity, the selection output from the first selection means including a negative polarity, a sum of the sum and selection result, and zero, wherein an xcex1 metric and xcex2 metric are calculated on the basis of an output from the second selection means.